Methodology of Selecting Scan-based Testability Improving Technique
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چکیده
In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.
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تاریخ انتشار 2005